Abstract
PURPOSE: To realize a synchronization circuit operated accurately anc stably in the spread spectrum multiple address (SSMA) communication.
CONSTITUTION: A received signal sampled by a sampler 104 is given to a digital matched filter (DMF) 105 in which correlation is detected and a comparator 108 compares levels of detection outputs for each sample within a symbol period from an envelope detector 106 and sample positions (phases) by a prescribed sample number decided in advance are stored in a memory circuit 109 in the order of higher outputs. Then the stored number of times of the stored sample positions is counted by a memory circuit 110 for each symbol period and a detection circuit 111 detects a sample position of the largest count as a peak position and a setting circuit 112 sets the acquisition/holding and reception window position of the symbol synchronization based on the peak position.
COPYRIGHT: (C)1996JPO&Japio
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Wireless communication
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SUMMARY
ClaimChart-JPH08116293A-STO
Patent number:JPH08116293A
Claim Chart Type : SEP Claim Chart
Price: 200 €
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The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
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Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
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