Abstract
An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.
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3G | 14/03/2007 | ISLD-200708-008 | QUALCOMM INC | No | Family Member | ||||
Not Available | 14/03/2007 | ISLD-200708-008 | QUALCOMM INC |
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Not Available | 23/04/2008 | ISLD-200804-012 | QUALCOMM INC |
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