Abstract
A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. In the interchanging when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol a (#i +1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i a (#i +1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i and a bit b 0 a bit b1 and a bit b2 are interchanged with a bit y1 a bit y0 and a bit y2.
Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | |||||
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Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP | Yes | Family Member | ||||
Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP | No | Family Member |
Specification Information
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EP2993793A1 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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EP2993793A1 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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EP2993793A4 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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EP2993793A4 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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CN105144589A | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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CN105144589A | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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JP6229899B2 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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JP6229899B2 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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JPWO2014178296A1 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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JPWO2014178296A1 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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RU2015145970A | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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RU2015145970A | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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RU2015145970A3 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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RU2015145970A3 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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RU2658791C2 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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RU2658791C2 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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US9859922B2 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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US9859922B2 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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WO2014178296A1 | Not Available | 01/11/2018 | ISLD-201812-050 | SONY CORP |
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WO2014178296A1 | Not Available | 17/05/2021 | ISLD-202105-013 | SONY CORP |
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Technologies
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Use Cases
Services
Claim
1-40. (canceled)
41: A data processing device comprising:
an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15; and an interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges a bit b0 with a bit y1, a bit b1 with a bit y0, and a bit b2 with a bit y2, wherein the LDPC code includes an information bit and a parity bit, wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit, wherein the information matrix part is shown by a parity check matrix initial value table, and wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows 3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638 356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602 18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6 412 6753 7169 7524 7695 7976 8069 8118 8522 8582 714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559 3452 7935 8092 8623 56 1955 3000 8242 1809 4094 7991 8489 2220 6455 7849 8548 1006 2576 3247 6976 2177 6048 7795 8295 1413 2595 7446 8594 2101 3714 7541 8531 10 5961 7484 3144 4636 5282 5708 5875 8390 3322 5223 7975 197 4653 8283 598 5393 8624 906 7249 7542 1223 2148 8195 976 2001 5005.
42: The data processing device according to claim 41,
wherein the interchanging unit interchanges a code bit of 3�1 bits of the LDPC code that is written in a column direction and read in a row direction of a storage unit including three columns that store 3�1 bits in the row direction and that store 16200/(3�1) bits in the column direction.
43: A data processing method comprising:
an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15; and an interchanging step of interchanging a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, wherein, in the interchanging step, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2, wherein the LDPC code includes an information bit and a parity bit, wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit, wherein the information matrix part is shown by a parity check matrix initial value table, and wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows 3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638 356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602 18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6 412 6753 7169 7524 7695 7976 8069 8118 8522 8582 714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559 3452 7935 8092 8623 56 1955 3000 8242 1809 4094 7991 8489 2220 6455 7849 8548 1006 2576 3247 6976 2177 6048 7795 8295 1413 2595 7446 8594 2101 3714 7541 8531 10 5961 7484 3144 4636 5282 5708 5875 8390 3322 5223 7975 197 4653 8283 598 5393 8624 906 7249 7542 1223 2148 8195 976 2001 5005.
44: A data processing device comprising:
an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15; and an interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 16 signal points defined by 16APSK, wherein, when 4 bits of code bits stored in four units of storages having a storage capacity of 16200/4 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 4 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 4 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges a bit b0 with a bit y2, a bit b1 with a bit y1, a bit b2 with a bit y0, and a bit b3 with a bit y3, wherein the LDPC code includes an information bit and a parity bit, wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit, wherein the information matrix part is shown by a parity check matrix initial value table, and wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows 3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638 356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602 18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6 412 6753 7169 7524 7695 7976 8069 8118 8522 8582 714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559 3452 7935 8092 8623 56 1955 3000 8242 1809 4094 7991 8489 2220 6455 7849 8548 1006 2576 3247 6976 2177 6048 7795 8295 1413 2595 7446 8594 2101 3714 7541 8531 10 5961 7484 3144 4636 5282 5708 5875 8390 3322 5223 7975 197 4653 8283 598 5393 8624 906 7249 7542 1223 2148 8195 976 2001 5005.
45: The data processing device according to claim 44,
wherein the interchanging unit interchanges a code bit of 4�1 bits of the LDPC code that is written in a column direction and read in a row direction of a storage unit including four columns that store 4�1 bits in the row direction and that store 16200/(4�1) bits in the column direction.
46: A data processing method comprising:
an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15; and an interchanging step of interchanging a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 16 signal points defined by 16APSK, wherein, in the interchanging step, when 4 bits of code bits stored in four units of storages having a storage capacity of 16200/4 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 4 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 4 bits of symbol bits of the one symbol is set to a bit y#i, a bit b0 is interchanged with a bit y2, a bit b1 is interchanged with a bit y1, a bit b2 is interchanged with a bit y0, and a bit b3 is interchanged with a bit y3, wherein the LDPC code includes an information bit and a parity bit, wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit, wherein the information matrix part is shown by a parity check matrix initial value table, and wherein the parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part for every 360 columns and is expressed as follows 3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638 356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602 18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6 412 6753 7169 7524 7695 7976 8069 8118 8522 8582 714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559 3452 7935 8092 8623 56 1955 3000 8242 1809 4094 7991 8489 2220 6455 7849 8548 1006 2576 3247 6976 2177 6048 7795 8295 1413 2595 7446 8594 2101 3714 7541 8531 10 5961 7484 3144 4636 5282 5708 5875 8390 3322 5223 7975 197 4653 8283 598 5393 8624 906 7249 7542 1223 2148 8195 976 2001 5005.
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The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
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Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
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