Abstract
A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.
Technologies
Product
Use Cases
Services
Claim
1. A method for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream comprising a multiplicity of 8 bit data blocks, said method including partitioning the 8 bit block into two sub-blocks consisting of 5 and 3 contiguous bits, examining each sub-block to determine if any of the individual bits require alteration and altering predetermined bits based on said determination to produce an alternate code pattern, determining the disparity (D0) of the current output sub-block being coded, ascertaining the disparity (D-1) of the last non-zero sub-block coded and selecting a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity in the output code pattern was of a first polarity, assigning the complement of said first code pattern if the last non-zero disparity was of the opposite polarity.
2. A coding method as set forth in claim 1, wherein the encoding of the 5 bit input data sub-block and the 3 bit input data sub-block is performed substantially concurrently.
3. A coding method as set forth in claim 2 including automatically adding an extra bit of a predetermined value to each input sub-block to form each output sub-block, said predetermined value being subject to change if it is determined that a predetermined code pattern in said current input sub-block requires changing said extra bit.
4. A coding method as set forth in claim 3 wherein said alternate code pattern is generated by controlling the complementation of individual bits of said input sub-block and said extra bit in accordance with the logical content thereof to alter same when necessary.
5. A coding method as set forth in claim 4 wherein the selection of the particular input bits to be complemented is accomplished by logically combining individual predetermined bits of said input data sub-block.
6. A coding method as set forth in claim 5 wherein the step of computing the disparity of a current sub-block includes the steps of performing a logic analysis of the input bits of said current sub-block and the output of the bit encoding step to determine the disparity of the current sub-block.
7. A coding method as set forth in claim 6 including the step of notifying the coding system when a specific input 8 bit block is to be representative of a special character outside of the domain of the normal 256 characters representable by the 8 bit code pattern and producing specially encoded output sub-blocks whenever such special character indication accompanies a given 8 bit input sub-block.
8. A coding method as set forth in claim 7 including factoring said special character indication (K bit) into said bit encoding and disparity determining steps for the 3 bit input sub-block, whereby all of the 4 bit encoded sub-blocks for the special characters have an alternate form which is assigned based solely on a determination of the last non-zero disparity (D-1) sub-block.
9. A coding method as set forth in claim 8 wherein the step of encoding said special character sub-blocks distinctly from encoded data sub-blocks, includes determining if a predetermined run length and disparity is present in the immediately preceding output sub-block and providing a first output sub-block for such special character if said predetermined run length is present and a second output sub-block if said predetermined run length is not present
10. A coding method as set forth in claim 9 wherein the step of providing said second output sub-block comprises complementing said first output sub-block in accordance with both a run length and disparity determination
11. A binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, means for testing each input sub-block to determine if any of the individual bits require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (D0) of the current output sub-block being coded, means for determining the disparity (D-1) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the output sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said first code pattern if the last non-zero disparity sub-block was of the opposite polarity
12. A data encoding apparatus as set forth in claim 11 wherein said means for partitioning includes means for gating the 3 bit and 5 bit input data sub-blocks into the encoding apparatus for substantially concurrent encoding
13. A data encoding apparatus as set forth in claim 12 including means for concatenating an extra bit of a predetermined value at the end of each input data sub-block to form each encoded output sub-block, and means for changing the predetermined value of said extra bit if it is found that a predetermined bit pattern is present in said current data input sub-block
14. A data encoding apparatus as set forth in claim 13 wherein the means for generating the complement of said first code pattern comprises means for combining the output of said testing means and in said disparity determining means do produce a complementation signal which causes the complement of said first code pattern generated by the system to be gated to the output thereof as the encoded output sub-block
15. A data encoding apparatus as set forth in claim 14 wherein said means for complementing includes means for evaluating all of the input data bits of both sub-blocks and also the polarity (negative or positive) of the last non-zero encoded sub-block
16. A data encoding apparatus as set forth in claim 15 wherein the means for determining the disparity (D0) of the current sub-block includes means for logically combining the input bits of said current sub-block with the output of the testing means to determine if the disparity of the current sub-block (D0) is zero, positive or negative
17. A data encoding apparatus as set forth in claim 16 including means for indicating that a particular 8 bit input block is a special character outside of the domain of the 256 characters normally representable by the 8 bit input data block and means actuable in response to said indication for producing a specially encoded 4 bit output sub-block from said input 8 bit block whenever such special character indication accompanies a given 8 bit input block
18. A data encoding apparatus as set forth in claim 17 wherein the means for encoding said special character 3 bit sub-block distinctly from a 3 bit data character input sub-block includes means for determining if a predetermined run length is present in the immediately preceding encoded 6 bit output sub-block for the associated 5 bit data input block and for providing a first 4 bit encoded output sub-block for such special character if said predetermined run length is present and a different 4 bit coded output sub-block if said predetermined run length is not present
19. A data encoding apparatus as set forth in claim 18 wherein the means for providing said different 4 bit coded sub-block includes means for complementing said first encoded 4 bit output sub-block.
20. A binary data encoding apparatus for producing a DC balanced (0,4) run length limited rate 8B/10B code from an unconstrained input data stream including means for supplying consecutive 8 bit data blocks to said apparatus, means for partitioning the 8 bit input block into two sub-blocks consisting of 5 and 3 contiguous bits, said partitioning means including means for gating the 3 bit and 5 bit input data sub-blocks into the encoding apparatus for substantially concurrent encoding in separate circuitry provided for each sub-block, means for concatenating an extra bit of a predetermined value at the end of each input data sub-block to form the additional bit of each encoded output sub-block, means for testing each input sub-block to determine if any of the individual bits or the extra bit require alteration during encoding and altering predetermined bits based on said determination to produce an alternate code pattern from said input bit pattern, means for determining the disparity (D0) of the current output sub-block being coded including means for logically combining the input bits of said current input sub-block with the output of the testing and altering means to determine if the disparity of the current sub-block (D0) is zero, positive or negative, means for determining the disparity (D-1) of the last non-zero sub-block coded and generating a first code pattern as the current output sub-block for certain of the input sub-blocks if the last non-zero disparity sub-block in the output code stream was of a first polarity, means for generating the complement of said first code pattern if the last non-zero disparity sub-block was of the opposite polarity, said complementing means including means for evaluating all of the input data bits of both sub-blocks and also the polarity (negative or positive) of the last non-zero encoded sub-block.']
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SUMMARY
ClaimChart-US4486739A-STO
Patent number:US4486739A
Claim Chart Type : SEP Claim Chart
Price: 200 €
Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.