Abstract
A decoder is arranged to operate as a single-bit error correction circuit (ECC) and as a multiple-bit error detection circuit (EDC). The decoder starts and remains in the ECC state as long as no errors are detected in a received data message. When an error is detected or corrected in a received data message, the decoder switches to the EDC state where it remains as long as errors are detected in the received data message. When no errors are detected in the received data message, the decoder switches back to the ECC state. In a generalized multistate decoder, switching occurs from one state to another state, each state having a different error correcting capability, in response to a predetermined number of errors corrected or detected in the received data.
Technologies
Product
Use Cases
Services
Claim
No claims available.
Associated Portfolios
Licensor Claim Chart
 Claim Chart |
 Technology |
 Creation Date |
 Download |
|---|---|---|---|
|
Claim charts will soon be available!
|
|||
SUMMARY
ClaimChart-US4979174A-STO
Patent number:US4979174A
Claim Chart Type : SEP Claim Chart
Price: 200 €
Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.