US6345069B1

4G,3G

Title

Simplified cell search scheme for first and second stage

Application Number:

US19980217759

Publication Date:

05-02-2002

Current Assignee:

INTEL CORP

Family ID:

26801651

Application Date:

21-12-1998

Publication Country:

US

View on Espacenet

Priority Date:

16-10-1998

Declaring Company:

INTEL CORP , TEXAS INSTRUMENTS INC

Abstract  Abstract

A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit ( 121) has N taps ( 142-146) arranged to produce a respective plurality of first tap signals from the input signal ( 111). A first logic circuit ( 130 132 134 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal ( 150) in response to the clock signal the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps ( 150 172-184) arranged to produce a respective plurality of second tap signals from the first output signal wherein a ratio of N/M is no greater than four. A second logic circuit ( 186) is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal ( 188) in response to the one of a true and a complement of each of the plurality of second tap signals.

Note:

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