US6356605B1

4G,3G

Title

Frame synchronization in space time block coded transmit antenna diversity for WCDMA

Application Number:

US19980195942

Publication Date:

12-03-2002

Current Assignee:

INTEL CORP

Family ID:

26800404

Application Date:

19-11-1998

Publication Country:

US

View on Espacenet

Priority Date:

07-10-1998

Declaring Company:

INTEL CORP , TEXAS INSTRUMENTS INC

Abstract  Abstract

A circuit is designed with a correction circuit ( 350) coupled to receive a first estimate signal (? j1) a second estimate signal (? j2) and a plurality of input signals from an external source along plural signal paths. The plurality of input signals includes a first and a second input signal (R j 1 R j2) The correction circuit produces a first symbol estimate in response to the first and second estimate signals and the first and second input signals. The correction circuit produces a second symbol estimate in response to the first and second estimate signals and the first and second input signals. A combining circuit is coupled to receive a plurality of first symbol estimates including the first symbol estimate and a plurality of second symbol estimates including the second symbol estimate. The combining circuit produces a first symbol signal ({tilde over (S)} 1) in response to the plurality of first symbol estimates and a second symbol signal ({tilde over (S)} 2) in response to the plurality of second symbol estimates. A synchronization circuit ( 408) is coupled to receive the first and second symbol signals ( 400-406) and a first known symbol and a second known symbol ( 410-416). The synchronization circuit produces a synchronization signal ( 418) in response to an approximate match between the first symbol signal and the first known symbol and between the second symbol signal and the second known symbol.

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