Abstract
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping the read-out being in a different order than the read-in the order being determined from a set of addresses with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
| Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | |||||
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| Declaration Date | Declaration Reference | Declaring Company | Specification Information | ||||||
| Not Available | 13/01/2009 | ISLD-200902-010 | SONY CORP |
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Specification Information
Specification Information
Technologies
Family Information
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| Publication No | Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | Status | National Phase Entries | |||||
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Technologies
Signal Processing
Product
Use Cases
Mobile TV/ Radio
Services
Claim
1. A data processing apparatus configured to map symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus, comprising:
a de-interleaver configured to read-into a memory a predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols to indicate the OFDM sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, the address generator including
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial, and
an address check circuit configured to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately eight thousand, and
the linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R?i [11]=R?i-1[0]?R?i-1[1]?R?i-1[4]?R?i-1[6], that is configured to form, with an additional bit, a thirteen bit address Ri [n] for the i-th data symbol from the bit present in the n-th register stage Ri[n] and wherein the address generator comprises an offset generator configured to add an offset to the formed 13 bit address.
2. The data processing apparatus as claimed in claim 1, wherein the offset generator is configured to add the offset to the formed thirteen bit address modulo the predetermined number of sub-carrier symbols.
3. The data processing apparatus as claimed in claim 1, wherein the offset generator generates the offset using another address generator.
4. The data processing apparatus as claimed in claim 1, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the other address generator used by the offset generator to generate the offset is an address generator for one of the plurality of operating modes.
5. The data processing apparatus as claimed in claim 1, wherein the OFDM symbol includes pilot sub-carriers which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the sub-carrier pilot symbols present in the OFDM symbol.
6. The data processing apparatus as claimed in claim 1, wherein the predetermined maximum valid address is a value substantially between six thousand and eight thousand one hundred and ninety two.
7. The data processing apparatus as claimed in claim 1, where the address generator further comprises a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers.
8. The data processing apparatus a claimed in claim 3, wherein the another address generator forms a 13 bit address using a toggle value.
9. The data apparatus as claimed in claim 4, wherein the other address generator is the address generator for the 16k operating mode.
10. The data processing apparatus as claimed in claim 7, wherein the address generator further comprises a control circuit which is configured to re generate an address in combination with the address check circuit.
11. The data processing apparatus as claimed in claim 7, wherein the permutation circuit is configured to change a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
12. The data processing apparatus according to claim 10, wherein the linear feedback shift register is configured to generate the thirteen bit address in accordance with a code defined by the table:
R?i bit positions
11
10
9
8
7
6
5
4
3
2
1
0
Ri bit
5
11
3
0
10
8
6
9
2
4
1
7
positions.
13. The data processing apparatus as claimed in claim 10, wherein the offset generator is configured to add the offset to the formed thirteen bit address modulo the predetermined number of sub-carrier symbols.
14. The data processing apparatus as claimed in claim 10, wherein the offset generator generates the offset using another address generator.
15. A method of mapping symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the method, comprising:
reading into a memory a predetermined number of data symbols from the OFDM sub-carrier signals,
reading-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and
generating the set of addresses, an address being generated for each of the received symbols to indicate the OFDM sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, the step of generating the set of addresses including
using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, and
re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein
the predetermined maximum valid address is approximately eight thousand, and
the linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R?i [11]=R?i-1[0]?R?i-1[1]?R?i-1[4]?R?i-1[6], and the permutation order forms, with an additional bit, a thirteen bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage Ri[n] and adding by offset generator circuitry an offset to the formed 13 bit address.
16. The method as claimed in claim 15, wherein the adding the offset comprises adding the offset to the formed thirteen bit address modulo the predetermined number of sub-carrier symbols.
17. The method as claimed in claim 15, wherein the generating addresses comprises using a differently configured linear feedback shift register of an address generator to form, with a toggle value, a 13 bit address.
18. The method as claimed in claim 15, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the adding the offset comprises generating an address for another of the plurality of operating modes using the differently configured linear feedback shift register of an address generator.
19. The method as claimed in claim 15, wherein the OFDM symbol includes pilot sub-carriers which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the sub-carrier pilot symbols present in the OFDM symbol.
20. The method as claim in claim 15, wherein the predetermined maximum valid address is a value substantially between six thousand and eight thousand one hundred and ninety two.
21. The method as claimed in claim 15, further comprising using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address.
22. The method as claimed in claim 18, wherein the another operating mode is the 16k operating mode.
23. The method according to claim 18, wherein the linear feedback shift register generates the thirteen bit address in accordance with a code defined by the table:
R?i bit positions
11
10
9
8
7
6
5
4
3
2
1
0
Ri bit
5
11
3
0
10
8
6
9
2
4
1
7
positions.
24. The method as claimed in claim 18, wherein the adding the offset comprises adding the offset to the formed thirteen bit address modulo the predetermined number of sub-carrier symbols.
25. The method as claimed in claim 18, wherein the predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the adding the offset comprises generating an address for another of the plurality of operating modes.
26. The method as claimed in claim 18, comprising changing a permutation code, which permutes the order of the bits of the register stages to form the addresses from one OFDM symbol to another.
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The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.