Abstract
A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are interleaved.
Technologies
Broadcast/Multicast
Product
Use Cases
Mobile TV/ Radio
Services
Claim
1. A method for interleaving, comprising:
in a processor:
interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and
interleaving the one or more interlaces such that the mapped symbols are interleaved into a second order.
2. The method of claim 1, wherein the bit reversal fashion is a reduced-set bit reversal operation if the number of subcarriers is not a power of two.
3. The method of claim 2, wherein the interleaving is in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes.
4. The method of claim 1, wherein the interleaving is in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes.
5. The method of claim 2, wherein interleaving subcarriers comprises:
creating an empty subcarrier index vector (SCIV);
initializing an index variable (i) to zero;
converting i to its bit reversed nine-bit value (ibr);
appending ibr into the SCIV, if ibr is less than 511; and
incrementing i by one and repeating the converting, appending and incrementing, if i is less than 511.
6. The method of claim 5, wherein interleaving the one or more interlaces comprises:
for a 1K FFT size, mapping interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=BR2(SCIV[i] mod 4),
j=floor(SCIV[i]/4), and
BR2(*) is a bit reversal operation for two bits.
7. The method of claim 5, wherein interleaving the one or more interlaces comprises:
for a 2K FFT size, mapping interlaces in 2 consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=(SCIV[i] mod 2), and
j=floor(SCIV[i]/2).
8. The method of claim 5, wherein interleaving the one or more interlaces comprises:
for a 4K FFT size, mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to an interlace subcarrier with index SCIV[i].
9. The method of claim 5, wherein the interleaving the one or more interlaces comprises:
for an 8K FFT size, mapping an ith modulation symbol, where i?(0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
s is a slot to which OFDM symbols are mapped,
j=2�SCIV[i], if the slot belongs to an odd MAC time unit, and
j=2�SCIV[i]+1, if the slot belongs to an even MAC time unit.
10. The method of claim 1, wherein the number of interlaces is eight.
11. The method of claim 1, wherein interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table.
12. The method of claim 1, wherein interleaving the one or more interlaces occurs every OFDM symbol.
13. A processor configured to:
interleave subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and
interleave the one or more interlaces such that the mapped symbols are interleaved into a second order.
14. The processor of claim 13, wherein the processor is in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes.
15. A processor in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising:
means for interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and means for interleaving the one or more interlaces such that the mapped symbols are interleaved into a second order.
16. A non-transitory computer-readable medium storing instructions causing a processor to execute a method, comprising:
interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; and
interleaving the one or more interlaces such that the mapped symbols are interleaved into a second order.
17. The processor of claim 13, wherein interleaving subcarriers comprises:
creating an empty subcarrier index vector (SCIV);
initializing an index variable (i) to zero;
converting i to its bit reversed nine-bit value (ibr);
appending ibr into the SCIV, if ibr is less than 511; and
incrementing i by one and repeating the converting, appending and incrementing, if i is less than 511.
18. The processor of claim 17, wherein interleaving the one or more interlaces comprises:
for a 1K FFT size, mapping interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=BR2 (SCIV[i] mod 4),
j=floor(SCIV[i]/4), and
BR2(*) is a bit reversal operation for two bits.
19. The processor of claim 17, wherein interleaving the one or more interlaces comprises:
for a 2K FFT size, mapping interlaces in 2 consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=(SCIV[i] mod 2), and
j=floor(SCIV[i]/2).
20. The processor of claim 17, wherein interleaving the one or more interlaces comprises:
for a 4K FFT size, mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to an interlace subcarrier with index SCIV[i].
21. The processor of claim 17, wherein interleaving the one or more interlaces comprises:
for an 8K FFT size, mapping an ith modulation symbol, where i?(0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
is a slot to which OFDM symbols are mapped,
j=2�SCIV[i], if the slot belongs to an odd MAC time unit, and
j=2�SCIV[i]+1, if the slot belongs to an even MAC time unit.
22. The processor of claim 13, wherein interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table.
23. The processor of claim 15, wherein the means for interleaving subcarriers comprises:
means for creating an empty subcarrier index vector (SCIV);
means for initializing an index variable (i) to zero;
means for converting i to its bit reversed nine-bit value (ibr);
means for appending ibr into the SCIV, if ibr is less than 511; and
means for incrementing i by one and repeating the converting, appending and incrementing, if i is less than 511.
24. The processor of claim 23, wherein the means for interleaving the one or more interlaces comprises:
for a 1K FFT size, means for mapping interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=BR2 (SCIV[i] mod 4),
j=floor(SCIV[i]/4), and
BR2(*) is a bit reversal operation for two bits.
25. The processor of claim 23, wherein the means for interleaving the one or more interlaces comprises:
for a 2K FFT size, means for mapping interlaces in 2 consecutive OFDM symbols to slot by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=(SCIV[i] mod 2), and
j=floor(SCIV[i]/2).
26. The processor of claim 23, wherein the means for interleaving the one or more interlaces comprises:
for a 4K FFT size, means for mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to an interlace subcarrier with index SCIV[i].
27. The processor of claim 23, wherein the means for interleaving the one or more interlaces comprises:
for an 8K FFT size, means for mapping an ith modulation symbol, where i?(0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
s is a slot to which OFDM symbols are mapped,
j=2�SCIV[i], if the slot belongs to an odd MAC time unit, and
j=2�SCIV[i]+1, if the slot belongs to an even MAC time unit.
28. The processor of claim 15, wherein the means for interleaving subcarriers of one or more interlaces in a bit reversal fashion further comprises means for mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table.
29. The computer-readable medium of claim 16, wherein interleaving subcarriers comprises:
creating an empty subcarrier index vector (SCIV);
initializing an index variable (i) to zero;
converting i to its bit reversed nine-bit value (ibr);
appending ibr into the SCIV, if ibr is less than 511; and
incrementing i by one and repeating the converting, appending and incrementing, if i is less than 511.
30. The computer-readable medium of claim 29, wherein interleaving the one or more interlaces comprises:
for a 1K FFT size, mapping interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=BR2 (SCIV[i] mod 4),
j=floor(SCIV[i]/4), and
BR2(*) is a bit reversal operation for two bits.
31. The computer-readable medium of claim 29, wherein interleaving the one or more interlaces comprises:
for a 2K FFT size, mapping interlaces in 2 consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
k=(SCIV[i] mod 2), and
j=floor(SCIV[i]/2).
32. The computer-readable medium of claim 29, wherein interleaving the one or more interlaces comprises:
for a 4K FFT size, mapping an ith modulation symbol, where i?{0, 1, . . . , 499}, to an interlace subcarrier with index SCIV[i].
33. The computer-readable medium of claim 29, wherein interleaving the one or more interlaces comprises:
for an 8K FFT size, mapping an ith modulation symbol, where i?(0, 1, . . . , 499}, to a jth subcarrier of interlace Ik(s), wherein
is a slot to which OFDM symbols are mapped,
j=2�SCIV[i], if the slot belongs to an odd MAC time unit, and
j=2�SCIV[i]+1, if the slot belongs to an even MAC time unit.
34. The computer-readable medium of claim 16, wherein interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table.
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Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
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