Abstract
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits an interleaver circuit for interleaving parity bits within each group of parity bits and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.
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Technologies
Resource configuration Channel Arrangement/Coding
Product
Base Station (eNB/gNB)User Equipment (UE/Terminal)
Use Cases
Wireless communication
Services
Error correction/detection
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SUMMARY
Total no of independent claims: 5
Total no of independent claims analysed: 5
Independent Claim Number
TS Mapped
1
TS 38.212 v15.0.0
6
TS 38.212 v15.0.0
8
TS 38.212 v15.0.0
12
TS 38.212 v15.0.0
14
TS 38.212 v15.0.0
ClaimChart-US9467176B2
Patent number:US9467176B2
Claim Chart Type : SEP Claim Chart
Technology: 5G
Price: 200 €
SUMMARY
Total no of independent claims: 5
Total no of independent claims analysed: 5
Independent Claim Number
TS Mapped
1
TS 38.212 v15.0.0
6
TS 38.212 v15.0.0
8
TS 38.212 v15.0.0
12
TS 38.212 v15.0.0
14
TS 38.212 v15.0.0
ClaimChart-US9467176B2
Patent number:US9467176B2
Claim Chart Type : SEP Claim Chart
Technology: 5G
Price: 200 €
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The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.
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