Abstract
A method for transmitting and receiving Uplink Control Information (UCI) a terminal and a base station are provided. The transmitting method includes: calculating the number (Q?) of modulation symbols occupied by the UCI to be transmitted; dividing the information bit sequence of the UCI to be transmitted into two parts; using Reed Muller (RM) (32 0) codes to encode each part of information bit sequence of the UCI to be transmitted to obtain a 32-bit coded bit sequence respectively and performing rate matching so that the rate of the first 32-bit coded bit sequence is ?Q?/2?xQ m bits and that the rate of the second 32-bit coded bit sequence is (Q???Q?/2?)xQm bits; and mapping the two parts of coded bit sequences that have undergone rate matching onto a Public Uplink Shared Channel (PUSCH) and transmitting the coded bit sequences to a base station.
| Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | |||||
|---|---|---|---|---|---|---|---|---|---|
| Declaration Date | Declaration Reference | Declaring Company | Specification Information | ||||||
| 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
Specification Information
Specification Information
Technologies
Family Information
| All Granted Patents In Patent Family : | ---- |
| Publication No | Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| Declaration Date | Declaration Reference | Declaring Company | Specification Information | |||||||
| CN102468917A | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
Yes | Basis Patent | |||
| CN102468917B | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
Yes | Basis Patent | |||
| EP2445133A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| EP2445133A4 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| EP2445133B1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| EP2753015A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| ES2513596T3 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US2012134306A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US8619633B2 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US2014092846A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US9014057B2 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US2015195832A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US9491745B2 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US2017079030A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| WO2011147382A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| US2018077701A1 | 5G | 25/12/2017 | ISLD-201711-019 | HUAWEI |
S1
S2
S3
S4
S5
|
No | Family Member | |||
| EP2753015B1 | ----- | ----- | ----- | ----- | ----- | ----- | ----- | |||
| EP3373490B1 | ----- | ----- | ----- | ----- | ----- | ----- | ----- | |||
| US10306608B2 | ----- | ----- | ----- | ----- | ----- | ----- | ----- | |||
| Publication No | Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | Status | National Phase Entries | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Declaration Date | Declaration Reference | Declaring Company | Specification Information | |||||||||
| ----- | ----- | ----- | ----- | ----- |
S1
|
----- | ----- | ----- | ----- | |||
Technologies
Resource configuration Channel Arrangement/Coding
Product
User Equipment (UE/Terminal)Base Station (eNB/gNB)
Use Cases
Wireless communication
Services
UCI transmission
Claim
1. A method for transmitting Uplink Control Information, comprising:
calculating, by a processor, the number of modulation symbols Q?, wherein the modulation symbols are occupied by the Uplink Control Information (UCI) to be transmitted;
dividing, by the processor, an information bit sequence of the UCI to be transmitted into a first information bit sequence and a second information bit sequence;
using, by the processor, a Reed Muller (RM) (32, O) code to encode the first information bit sequence to obtain a first 32-bit coded bit sequence; using a RM (32, O) code to encode the second information bit sequence to obtain a second 32-bit coded bit sequence;
performing, by the processor, rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a ?Q?/2?�Qm bits coded bit sequence; performing rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence, wherein Qm is a modulation order corresponding to the UCI to be transmitted, and ? ? refers to rounding up;
mapping, by the processor, the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence onto a Physical Uplink Shared Channel (PUSCH); and
controlling, by the processor, a transmitter to transmit the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence to a base station.
2. The method according to claim 1, wherein
mapping, by the processor, the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence onto a Physical Uplink Shared Channel (PUSCH) comprise:
concatenating, by the processor, the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence to form a new bit sequence; and
mapping, by the processor, the new bit sequence onto the PUSCH.
3. The method according to claim 1, wherein
performing, by the processor, rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to ?Q?/2?�Qm bits coded bit sequence comprises:
according to qi=b(i mod32) (i=0, 1, . . . , (?Q?/2?�Qm?1)), performing, by the processor, rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to the ?Q?/2?�Qm bits coded bit sequence, wherein qi is the ?Q?/2?�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the first 32-bit coded bit sequence, On is a bit in the first information bit sequence, Mj,n is a basic sequence of RM (32, O) code, and O? is a number of bits of the first information bit sequence.
4. The method according to claim 1, wherein
performing, by the processor, rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence comprises:
according to qi=b(i mod32) (i=0,1, . . . , ((Q???Q?/2?)�Qm?1)), performing, by the processor, rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to the (Q???Q?/2?)�Qm bits coded bit sequence, wherein qi is the (Q???Q?/2?)�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the second 32-bit coded bit sequence, On is a bit in the second information bit sequence, Mj,n is a basic sequence of RM (32, O) code, and O? is a number of bits of the second information bit sequence.
5. A method for receiving Uplink Control Information, comprising:
receiving the Uplink Control Information from a terminal;
calculating the number of modulation symbols Q?, wherein the modulation symbols are occupied by the Uplink Control Information;
determining candidate control information bit sequences according to a number of bits of the Uplink Control Information;
dividing each candidate control information bit sequence into a first candidate information bit sequence and a second candidate information bit sequence;
using a Reed Muller (RM) (32, O) code to encode the first candidate control information bit sequence to obtain a first 32-bit coded bit sequence; using a RM (32, O) code to encode the second candidate information bit sequence to obtain a second 32-bit coded bit sequence;
performing rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a ?Q?/2?�Qm bits coded bit sequence; performing rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence, wherein Qm is modulation order corresponding to the Uplink Control Information, and ? ? refers to rounding up; and
detecting the Uplink Control Information by using the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence of each candidate control information bit sequence.
6. The method according to claim 5, wherein detection of the Uplink Control Information by using the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence of each candidate control information bit sequence comprises:
concatenating the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence of each candidate control information bit sequence to form a new bit sequence, and using the new bit sequence to detect the Uplink Control Information.
7. The method according to claim 5, wherein
performing rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence comprises:
according to qi=b(i mod32) (i=0, 1, . . . , (?Q??/2?�Qm?1)), performing rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to the ?Q?/2?�Qm bits coded bit sequence, wherein qi is the ?Q?/2?�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the first 32-bit coded bit sequence, On is a bit in the first candidate information bit sequence, Mj,n is a basic sequence of RM (32, O) code, and O? is a number of bits of the first candidate information bit sequence.
8. The method according to claim 5, wherein
performing rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence comprises:
according to qi=b(i mod32) (i=0, 1, . . . , ((Q???Q?/2?)�Qm?1)), performing rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence, wherein qi is the (Q???Q?/2?)�Qm bits coded bit sequence
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the second 32-bit coded bit sequence, On is a bit in the second candidate information bit sequence, Mj,n is a basic sequence of RM (32, O) code, and O? is the number of bits of the second candidate information bit sequence.
9. A device, comprising:
a processor configured to:
calculate the number of modulation symbols Q?, wherein the modulation symbols are occupied by Uplink Control Information (UCI) to be transmitted, and obtain a modulation order Qm corresponding to the UCI to be transmitted;
divide an information bit sequence of the UCI to be transmitted in the calculating module into a first information bit sequence and a second information bit sequence;
use a Reed Muller (RM) (32, O) code to encode the first information bit sequence to obtain a first 32-bit coded bit sequence; use a RM (32, O) code to encode the second information bit sequence to obtain a second 32-bit coded bit sequence;
perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a ?Q?/2?�Qm bits coded bit sequence; and perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence, wherein Qm is the modulation order corresponding to the UCI to be transmitted, and ? ? refers to rounding up;
map the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence onto a Physical Uplink Shared Channel (PUSCH), and
control a transmitter to transmit the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit to a base station.
10. The device according to claim 9, wherein
the processor being configured to map the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence onto the PUSCH comprises:
being configured to concatenate the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence to form a new bit sequence, map the new bit sequence onto the PUSCH.
11. The device according to claim 9, wherein the processor is further configured to obtain a bit On of the first candidate information bit sequence, a basic sequence Mj,n of the RM (32, O) code, and O? being the number of bits of the first information bit sequence;
in order to perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a ?Q?/2?�Qm bits coded bit sequence the processor is configured to:
perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to the ?Q?/2?�Qm bits coded bit sequence according to qi=b(i mod32) (i=0,1, . . . , (?Q?/2?�Qm?1)), wherein qi is the ?Q?/2?�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the first 32-bit coded bit sequence, and On, Mj,n, and O? are parameters obtained by the processor.
12. The device according to claim 9, wherein the processor is further configured to obtain a bit On of the second information bit sequence, a basic sequence Mj,n of the RM (32, O) code, and O? being the number of bits of the second information bit sequence; and
in order to perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence the processor is configured to:
perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to the (Q???Q?/2?)�Qm bits coded bit sequence according to qi=b(i mod32) (i=0, 1, . . . , ((Q???Q?/2?)�Qm?1)), wherein qi is the (Q???Q?/2?)�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the second 32-bit coded bit sequence, and On, Mj,n and O? are parameters obtained by the processor.
13. A base station, comprising:
a receiver configured to receive Uplink Control Information sent by a terminal; and
a processor configured to
calculate the number of modulation symbols Q?, wherein the modulation symbols are occupied by the Uplink Control Information, and obtain modulation order Qm corresponding to the Uplink Control Information;
determine candidate control information bit sequences according to the number of bits of the Uplink Control Information received by the receiver;
divide each candidate control information bit sequence determined by the determining module into a first candidate information bit sequence and a second candidate information bit sequence;
use a Reed Muller (RM) (32,O) code to encode the first candidate control information bit sequence to obtain a first 32-bit coded bit sequence; use a RM (32, O) code to encode the second candidate information bit sequence to obtain a second 32-bit coded bit sequence;
perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a ?Q?/2?�Qm bits coded bit sequence; and perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence, wherein Qm is modulation order corresponding to the Uplink Control Information, and ? ? refers to rounding up; and
detect the Uplink Control Information by using the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence of each candidate control information bit sequence.
14. The base station according to claim 13, wherein
in order to detect the Uplink Control Information the processor is configured to:
concatenate the ?Q?/2?�Qm bits coded bit sequence and the (Q???Q?/2?)�Qm bits coded bit sequence of each candidate control information bit sequence to form a new bit sequence, and use the new bit sequence to detect the Uplink Control Information.
15. The base station according to claim 13, wherein the processor is further configured to obtain a bit On of the first candidate information bit sequence, a basic sequence Mj,n of the RM (32, O) code, and O? being a number of bits of the first candidate information bit sequence;
in order to perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence the processor is configured to:
perform rate matching for the first 32-bit coded bit sequence by circular repetition to set the first 32-bit coded bit sequence to the ?Q?/2?�Qm bits coded bit sequence according to qi=b(i mod32) (i=0,1, . . . , (?Q?/2?�Qm?1)), wherein qi is the ?Q?/2?�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the first 32-bit coded bit sequence, and On, Mj,n and O? are parameters obtained by the processor.
16. The base station according to claim 13, wherein the processor is further configured to obtain a bit On of the second candidate information bit sequence, a basic sequence Mj,n of the RM (32, O) code, and O? being a number of bits of the second candidate information bit sequence; and
in order to perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to a (Q???Q?/2?)�Qm bits coded bit sequence the processor is configured to:
perform rate matching for the second 32-bit coded bit sequence by circular repetition to set the second 32-bit coded bit sequence to the (Q???Q?/2?)�Qm bits coded bit sequence according to qi=b(i mod32) (i=0, 1, . . . , ((Q???Q?/2?)�Qm?1)) wherein qi is the (Q???Q?/2?)�Qm bits coded bit sequence,
b
j
=
?
n
=
0
O
?
-
1
?
(
O
n
�
M
j
,
n
)
?
mod
?
?
2
(
j
=
0
,
1
,
�
?
,
31
)
?is the second 32-bit coded bit sequence, and On, Mj,n and O? are parameters obtained by the processor.
Associated Portfolios
Licensor Claim Chart
 Claim Chart |
 Technology |
 Creation Date |
 Download |
|---|---|---|---|
|
Claim charts will soon be available!
|
|||
To view claim charts you must become a Gold or Platinum Member.
Upgrade your subscriptionYou have reached the maximum number of patents which can be associated to your account per your subscription. If you wish to associate more patents
Please upgrade your subscription.Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.