Abstract
A method and apparatus for channel coding and rate matching of the Physical Uplink Control Channel (PUCCH) and the Physical Downlink Control Channel (PDCCH) is disclosed that uses convolutional encoding to code the control channels. Rate matching is performed using a circular buffer based rate matching algorithm. A rate matching module may contain a single interleaver or may alternatively comprise a plurality of sub-block interleavers. Interleaved coded bits may be stored in the circular buffer in an interlaced format or output streams from separate sub-block interleavers may be stored contiguously. When a plurality of sub-block interleavers are used different interleaving patterns may be used. Rate matching may use bit puncturing or repetition to match the rate of the available physical channel resource. Rate matched output bits may be interleaved using a channel interleaver.
Technologies
Resource configuration
Product
Use Cases
Wireless communication
Services
Claim
1. A method for coding and rate matching a control channel for use in wireless communications, the method comprising: receiving a code block, wherein a length of the code block is N bits; encoding the code block using a convolutional encoder to generate coded bits; and matching a number of coded bits to an available physical channel resource, wherein a number of bits that may be transmitted on the available physical channel resource is K bits.
2. The method of claim 1, wherein the convolutional encoder is a rate 1/2 convolutional encoder.
3. The method of claim 2, wherein the convolutional encoder uses tail biting.
4. The method of claim 2, wherein matching the number of coded bits to the available physical channel resource uses a circular buffer to store the coded bits.
5. The method of claim 4, wherein the circular buffer is read to the end of the circular buffer, then re-read from the beginning of the circular buffer when the number of generated coded bits is less than K bits.
6. The method of claim 4, wherein the first K bits are read from the circular buffer when the number of generated coded bits is greater than K bits.
7. The method of claim 2 wherein the generated coded bits are interleaved.
8. The method of claim 7, wherein the generated coded bits are interleaved using a single block interleaver.
9. The method of claim 7, wherein the generated coded bits are interleaved using two sub-block interleavers
10. The method of claim 9, wherein the interleaved generated coded bits are interlaced as they are stored in the circular buffer
11. The method of claim 9, wherein a generated bit stream corresponding to one of the sub-block interleavers is stored contiguously in the circular buffer
12. The method of claim 1, wherein the convolutional encoder is a rate 1/3 convolutional encoder
13. The method of claim 12, wherein the convolutional encoder uses tail biting
14. The method of claim 12, wherein matching the number of coded bits to the available physical channel resource uses a circular buffer to store the coded bits
15. The method of claim 14, wherein the circular buffer is read to the end of the circular buffer, then re-read from the beginning of the circular buffer when the number of generated coded bits is less than K bits
16. The method of claim 15, wherein the first K bits are read from the circular buffer when the number of generated coded bits is greater than K bits
17. The method of claim 12 wherein the generated coded bits are interleaved
18. The method of claim 17, wherein the generated coded bits are interleaved using a single block interleaver
19. The method of claim 17, wherein the generated coded bits are interleaved using three sub-block interleavers.
20. The method of claim 19, wherein the interleaved generated coded bits are interlaced as they are stored in the circular buffer.
21. The method of claim 19, wherein a generated bit stream corresponding to one of the sub-block interleavers is stored contiguously in the circular buffer.
22. A wireless transmit/receive unit (WTRU) for transmitting and receiving control channels in wireless communications, comprising: a convolutional encoder used to code the control channels; and a rate-matching module to rate match the control channels, wherein the rate-matching module comprises a circular buffer.
23. The WTRU of claim 22, wherein the convolutional encoder is a rate 1/2 convolutional encoder that generates 2- N coded bits from an N bit input block.
24. The WTRU of claim 22, further comprising a channel interleaver.
25. The WTRU of claim 22, wherein the rate-matching module is configured to output a first K bits of the circular buffer, where K is a number of bits that may be transmitted on an available physical channel resource, when 2- N is greater than K bits.
26. The WTRU of claim 22, wherein the rate-matching module is configured to begin re-reading at a beginning of the circular buffer when an end of the circular buffer is reached, until K bits have been read, where K is a number of bits that may be transmitted on an available physical channel resource, when 2-N is less than K bits.
27. The WTRU of claim 26, wherein the rate-matching module further comprises one block interleaver.
28. The WTRU of claim 26, wherein the rate-matching module further comprises two sub-block interleavers.
29. The WTRU of claim 28, wherein each of the two sub-block interleavers uses a different interleaving pattern.
30. The WTRU of claim 28, wherein an output bit stream from each of the two sub-block interleavers are interlaced bit by bit when stored in the circular buffer.
31. The WTRU of claim 28, wherein an output bit stream from each of the two sub-block interleavers are stored contiguously in the circular buffer.
32. The WTRU of claim 24, wherein the convolutional encoder is a rate 1/3 convolutional encoder that generates 3- N coded bits from an N bit input block.
33. The WTRU of claim 32, wherein the rate-matching module is configured to output a first K bits of the circular buffer, where K is a number of bits that may be transmitted on the available physical channel resource, when 3-N is greater than K bits.
34. The WTRU of claim 32, wherein the rate-matching module is configured to begin re-reading at a beginning of the circular buffer when an end of the circular buffer is reached, until K bits have been read, where K is a number of bits that may be transmitted on the available physical channel resource, when 3- N is less than K bits.
35. The WTRU of claim 32, wherein the rate-matching module further comprises one block interleaver.
36. The WTRU of claim 32, wherein the rate-matching module further comprises three sub-block interleavers.
37. The WTRU of claim 36, wherein each of the three sub-block interleavers uses a different interleaving pattern.
38. The WTRU of claim 36, wherein an output bit stream from each of the three sub-block interleavers are interlaced bit by bit when stored in the circular buffer.
39. The WTRU of claim 36, wherein an output bit stream from each of the three sub-block interleavers are stored contiguously in the circular buffer.
40. A base station for transmitting and receiving control channels in wireless communications, comprising: a convolutional encoder used to code the control channels; and a rate-matching module to rate match the control channels, wherein the rate-matching module comprises a circular buffer.
41. The base station of claim 40, further comprising a channel interleaver.
42. The base station of claim 40, wherein the convolutional encoder is a rate 1/2 convolutional encoder that generates 2-N coded bits from an N bit input block.
43. The base station of claim 42, wherein the rate-matching module is configured to output a first K bits of the circular buffer, where K is a number of bits that may be transmitted on an available physical channel resource, when 2-N is greater than K bits.
44. The base station of claim 42, wherein the rate-matching module is configured to begin re-reading at a beginning of the circular buffer when an end of the circular buffer is reached, until K bits have been read, where K is a number of bits that may be transmitted on an available physical channel resource, when 2-N is less than K bits.
45. The base station of claim 42, wherein the rate-matching module further comprises one block interleaver.
46. The base station of claim 42, wherein the rate-matching module further comprises two sub-block interleavers.
47. The base station of claim 46, wherein each of the two sub-block interleavers uses a different interleaving pattern.
48. The base station of claim 46, wherein an output bit stream from each of the two sub-block interleavers are interlaced bit by bit when stored in the circular buffer.
49. The base station of claim 46, wherein an output bit stream from each of the two sub-block interleavers are stored contiguously in the circular buffer.
50. The base station of claim 40, wherein the convolutional encoder is a rate 1/3 convolutional encoder that generates 3-N coded bits from an N bit input block.
51. The base station of claim 50, wherein the rate-matching module is configured to output a first K bits of the circular buffer, where K is a number of bits that may be transmitted on an available physical channel resource, when 3-N is greater than K bits.
52. The base station of claim 50, wherein the rate-matching module is configured to begin re-reading at a beginning of the circular buffer when an end of the circular buffer is reached, until K bits have been read, where K is a number of bits that may be transmitted on an available physical channel resource, when 3-N is less than K bits.
53. The base station of claim 50, wherein the rate-matching module further comprises one block interleaver.
54. The base station of claim 50, wherein the rate-matching module further comprises three sub-block interleavers.
55. The base station of claim 54, wherein each of the three sub-block interleavers uses a different interleaving pattern.
56. The base station of claim 54, wherein an output bit stream from each of the three sub-block interleavers are interlaced bit by bit when stored in the circular buffer.
57. The base station of claim 54, wherein an output bit stream from each of the three sub-block interleavers are stored contiguously in the circular buffer.']
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SUMMARY
ClaimChart-WO2008151061A1-STO
Patent number:WO2008151061A1
Claim Chart Type : SEP Claim Chart
Price: 200 €
Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.