Abstract
between the inter-sequence permutation turbo code system with variable length input. The invention claims an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving component for receiving an information bit sequence input a first outputting means for outputting a first code bit output a second outputting means for outputting a second code bit sequence output; the bit-adding means. it is coupled to the receiving means the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means between with the first output member; a second convolutional code encoder and inter-sequence permutation interleaver coupled between the bit-adding means between it and the second convolutional code encoder. The second convolutional code encoder is coupled permutation interleaver the sequence between the said second output member.
Technologies
Signal Processing
Product
Use Cases
Wireless communication
Services
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SUMMARY
ClaimChart-CN104320146A-STO
Patent number:CN104320146A
Claim Chart Type : SEP Claim Chart
Price: 200 €
Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.