Abstract
The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means. Further the ISP encoder comprises a third outputting means coupled to the bit-adding means to output a third code bit output or directly coupled to the receiving means. Alternatively the ISP encoder comprises a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.
| Technology | Declaration Information | Specification Information | Explicitly Disclosed | Patent Type | |||||
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| Declaration Date | Declaration Reference | Declaring Company | Specification Information | ||||||
| 4G | 07/03/2014 | ISLD-201403-007 | ACER INC | Yes | Basis Patent | ||||
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| US2007022353A1 | 4G | 07/03/2014 | ISLD-201403-007 | ACER INC | Yes | Basis Patent | ||||
| CN101136640A | 4G | 07/03/2014 | ISLD-201403-007 | ACER INC | Yes | Family Member | ||||
| EP1895666A1 | 4G | 07/03/2014 | ISLD-201403-007 | ACER INC | Yes | Family Member | ||||
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Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
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