Abstract
A digital demodulator and method for demodulating digital data representing a phase shift keyed (PSK) signal are provided. The demodulator comprises a phase detector automatic frequency controller automatic timing recovery controller data decoder and unique word detector. According to the method of the present invention a PSK signal is received and digitized to substantially remove the signals amplitude characteristics. The phase detector receives an input of the digital data and based upon transitions in the data from a high state to low state and from a low state to a high state provides phase estimates. The phase estimates are converted by the data decoder into binary data representing the symbols transmitted to form the PSK signal. A number of overlapping windows of digital data are used to determine phase estimates. The unique word detector receives an input of binary data from the data decoder and using a correlation technique identifies one set of windows which substantially maximizes synchronization of the demodulator with the received PSK signal. After the synchronizing window has been identified the automatic frequency controller monitors any frequency drift of the PSK signal and corrects the phase estimates based on the frequency error. The automatic timing recovery controller uses the corrected phase errors from early and late windows with respect to the synchronizing window to adjust the timing of the synchronizing window by advancing or delaying the demodulators symbol timing signal to further maximize synchronization with the received PSK signal.
Technologies
Power Control
Product
Use Cases
Wireless communication
Services
Claim
1. In a communication system in which a PSK signal having a unique word is transmitted, said communication system having a receiver capable of receiving said PSK signal in a plurality of window sets, said window sets being offset in time, said receiver generating phase estimates of the PSK signal so received and detecting said unique word in one of said window sets based on said phase estimates and defining the said window set as synchronizing windows, said receiver having a timing recovery controller for adjusting the timing of said synchronization windows to improve the reception of the PSK signal, said timing recovery controller comprising:an early error detector for receiving an input of phase estimates corresponding to a window set being offset in time prior to said synchronizing windows and defining said phase estimates so received as early phase estimates, said early error detector determining an early phase error of said early phase estimates based on a known set of phases of the PSK signal; a late error detector for receiving an input of phase estimates corresponding to a window set following the synchronizing windows in time and defining the phase estimates as late phase estimates, said late error detector determining a late phase error of said late phase estimates based on the known set of phases of the PSK signal; a first comparison means coupled to said early and late error detectors for receiving an input of said early and late phase errors, respectively, said first comparison means comparing said early and late phase errors and providing an output indicative of the comparison and defining said output as a window offset error; and a timing recovery processor interfaced with said first comparison means for generating based on said window offset error a timing adjust signal used to adjust the timing of the synchronizing windows.', 'an early error detector for receiving an input of phase estimates corresponding to a window set being offset in time prior to said synchronizing windows and defining said phase estimates so received as early phase estimates, said early error detector determining an early phase error of said early phase estimates based on a known set of phases of the PSK signal;', 'a late error detector for receiving an input of phase estimates corresponding to a window set following the synchronizing windows in time and defining the phase estimates as late phase estimates, said late error detector determining a late phase error of said late phase estimates based on the known set of phases of the PSK signal;', 'a first comparison means coupled to said early and late error detectors for receiving an input of said early and late phase errors, respectively, said first comparison means comparing said early and late phase errors and providing an output indicative of the comparison and defining said output as a window offset error; and', 'a timing recovery processor interfaced with said first comparison means for generating based on said window offset error a timing adjust signal used to adjust the timing of the synchronizing windows.
2. The timing recovery controller of claim 1, further comprising:an early threshold detector interfaced with the comparison means for determining whether the window offset error is greater than a first predetermined threshold, said first predetermined offset being indicative of a positive offset from the center of each of the synchronizing windows; a late threshold detector interfaced with the comparison means for determining whether the window offset error is greater than a second predetermined threshold, said second predetermined threshold being indicative of a negative offset from the center of each of the synchronizing windows; an early counter interfaced with said early threshold detector for maintaining an early count of each window offset error determined to be greater than said first predetermined threshold; a late counter interfaced with said late threshold detector for maintaining a late count of each window offset error determined to be greater than said second predetermined threshold; and a second comparison means interfaced with said early counter and said late counter and said timing recovery processor for comparing said early count and said late count at predefined times to produce an output of said comparison and defining said output as the window timing error; said timing recovery processor using said window timing error to generate said timing adjustment signal.', 'an early threshold detector interfaced with the comparison means for determining whether the window offset error is greater than a first predetermined threshold, said first predetermined offset being indicative of a positive offset from the center of each of the synchronizing windows;', 'a late threshold detector interfaced with the comparison means for determining whether the window offset error is greater than a second predetermined threshold, said second predetermined threshold being indicative of a negative offset from the center of each of the synchronizing windows;', 'an early counter interfaced with said early threshold detector for maintaining an early count of each window offset error determined to be greater than said first predetermined threshold;', 'a late counter interfaced with said late threshold detector for maintaining a late count of each window offset error determined to be greater than said second predetermined threshold; and', 'a second comparison means interfaced with said early counter and said late counter and said timing recovery processor for comparing said early count and said late count at predefined times to produce an output of said comparison and defining said output as the window timing error;', 'said timing recovery processor using said window timing error to generate said timing adjustment signal.
3. The timing recovery controller of claim 2, wherein the PSK signal comprises a sequence of symbols such that each symbol of said sequence is transmitted over a period of time defining a symbol interval, said window offset error being provided each symbol interval, said communication system transmitting said sequence of symbols during a period of time defining a slot such that said second comparison means provides an output at the end of each slot period, the timing recovery controller further comprising:a timing accumulator interfaced with said second comparison means for accumulating said window timing errors for a predetermined number of slots; and a threshold comparator interfaced with said timing accumulator for comparing the window timing error so accumulated with a predetermined error threshold and causing said timing recovery processor to generate said timing adjust signal when an absolute value of said accumulated window timing error exceeds said predetermined error threshold.', 'a timing accumulator interfaced with said second comparison means for accumulating said window timing errors for a predetermined number of slots; and', 'a threshold comparator interfaced with said timing accumulator for comparing the window timing error so accumulated with a predetermined error threshold and causing said timing recovery processor to generate said timing adjust signal when an absolute value of said accumulated window timing error exceeds said predetermined error threshold.
4. The timing recovery controller of claim 2, wherein at least one of said first and second comparison means is a subtractor.
5. The timing recovery controller of claim 2, further comprising:an adder interfaced with said early and said late counter for adding together said early and late counts to provide an output indicative of the signal quality of the PSK signal so received.', 'an adder interfaced with said early and said late counter for adding together said early and late counts to provide an output indicative of the signal quality of the PSK signal so received.
6. In a communication system in which a PSK signal comprising a sequence of symbols forming a unique word, each symbol of said sequence being transmitted over a period of time defining a symbol interval, said PSK signal being transmitted and subsequently received by a receiver in a plurality of window sets defined by said receiver, said window sets being offset in time, said receiver generating phase estimates of the PSK signal so received and detecting said unique word in one of said window sets based on said phase estimates and defining said one window set as synchronizing windows, a method for adjusting the timing of said synchronization windows to improve the reception of the PSK signal comprising the steps of:defining a window before each of said synchronizing windows as an early window; defining a window after each of said synchronizing windows as a late window; determining a phase offset for each of said early and late windows based on a known set of phases of the PSK signal and defining said respective offset as an early window offset and a late window offset; comparing said phase offset corresponding to said early window and said phase offset corresponding to said late window and producing based on said comparison an output defining a timing offset; and adjusting a timing of said synchronizing windows relative to said symbol interval, based on said timing offset.', 'defining a window before each of said synchronizing windows as an early window;', 'defining a window after each of said synchronizing windows as a late window;', 'determining a phase offset for each of said early and late windows based on a known set of phases of the PSK signal and defining said respective offset as an early window offset and a late window offset;', 'comparing said phase offset corresponding to said early window and said phase offset corresponding to said late window and producing based on said comparison an output defining a timing offset; and', 'adjusting a timing of said synchronizing windows relative to said symbol interval, based on said timing offset.', '7. The method of claim 6, wherein said PSK signal is received over a period of time defining a slot, the method further comprising the steps of:providing one timing offset after each slot in which said PSK signal is so received; accumulating said timing offsets for a predetermined number of slots; and said step of adjusting said timing of said synchronizing window being carried out only if an absolute value of said timing offsets so accumulated exceed a predetermined timing offset threshold.', 'providing one timing offset after each slot in which said PSK signal is so received;', 'accumulating said timing offsets for a predetermined number of slots; and', 'said step of adjusting said timing of said synchronizing window being carried out only if an absolute value of said timing offsets so accumulated exceed a predetermined timing offset threshold.', '8. The method of claim 7, wherein said step of adjusting said timing of said synchronizing window comprises the steps of:delaying said synchronizing window if an absolute value of said accumulated timing offset exceeds said predetermined timing offset threshold and said late window error is greater than said early window error; and advancing said synchronizing window if an absolute value of said accumulated timing offset exceeds said predetermined timing offset threshold and said early window error is greater than said late window error.', 'delaying said synchronizing window if an absolute value of said accumulated timing offset exceeds said predetermined timing offset threshold and said late window error is greater than said early window error; and', 'advancing said synchronizing window if an absolute value of said accumulated timing offset exceeds said predetermined timing offset threshold and said early window error is greater than said late window error.']
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SUMMARY
ClaimChart-US5625652A-STO
Patent number:US5625652A
Claim Chart Type : SEP Claim Chart
Price: 200 €
Note:
The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)
The information in grey was provided by the patent holder
The information in purple was extracted from the FrandAvenue
Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.
Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.
Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.
Family member:related patents or applications that share a common priority or original filing.