Abstract
Teachings presented herein provide a method and apparatus for processing input information bits for coding using a code such that the length of the information word formed from the input information bits matches a fixed information word length defined by the code. In at least one embodiment a coding circuit receives input information bits (and adds error protection bits as needed to make the information word length match the fixed information word length. The method and apparatus contemplate generating the error protection bits by sub-coding a subset of the input information bits (e.g. parity bit generation) thereby providing extra protection for that subset. These teachings allow the same code to be used for coding feedback or other information where the amount of information to be coded varies as a function of operating modes.
Technology
Resource configuration Signal Processing
Product
Base Station (eNB/gNB)User Equipment (UE/Terminal)
Use Cases
Wireless communication
Services
Error correction/detection
Claim
1. A method of coding information using a code having a fixed information word length, the method comprising:
receiving a number of input information bits less than the fixed information word length for forming an information word, the received input information bits being of one or more types;
adding error protection bits to the received input information bits to make an information word length of the information word match the fixed information word length of the code, said error protection bits generated for a prioritized subset of the received input information bits by sub-coding the prioritized subset, for subsequent further coding as part of the information word; and
coding the information word using the code to form a corresponding code word.
2. The method of claim 1, wherein the code is a systematic code.
3. The method of claim 2, wherein the systematic code is a punctured quadratic residual code.
4. The method of claim 1, further comprising generating the error protection bits as parity bits for the prioritized subset of input information bits.
5. The method of claim 1, wherein said receiving, adding, and coding are performed in a second mode of operation, and wherein in a first mode of operation the method further comprises receiving a number of input information bits equal to the fixed information word length for forming a different information word, refraining from adding error protection bits to those received input information bits for making an information word length of the different information word match the fixed information word length of the code, and coding the different information word using the code to form a corresponding code word.
6. The method of claim 5, wherein the first and second modes of operation comprise first and second modes of Multiple-Input-Multiple-Output (MIMO) operation in a Wideband Code Division Multiple Access (WCDMA) transceiver, and wherein the input information bits in the first mode of operation include a first number of channel quality information bits and in the second mode of operation include a reduced, second number of channel quality information bits.
7. The method of claim 6, wherein the input information bits in both the first and second modes of operation include a set of channel quality information bits and a set of antenna pre-coding information bits, wherein the channel quality information bits are prioritized over the antenna pre-coding information bits, and wherein said adding in the second mode of operation comprises adding error protection bits for all or a subset of the channel quality information bits.
8. The method of claim 1, wherein the input information bits comprise two or more types of information bits, with one type being prioritized over the other type or types.
9. The method of claim 8, wherein adding error protection bits comprises sub-coding all or a selected subset of the prioritized type of input information bits to produce the number of error protection bits needed to extend the information word length to match the fixed information word length.
10. The method of claim 8, further comprising generating the error protection bits as a function of all or a subset of the prioritized type of input information bits.
11. The method of claim 1, wherein the code comprises a �20 , 10� code having a code word length of twenty bits and a fixed information word length of ten bits, and wherein receiving input information bits for forming an information word comprises, in a first mode of operation, receiving ten information bits, thereby matching the fixed information word length, and, in a second mode of operation, receiving less than ten input information bits and adding error protection bits as additional information bits to thereby obtain ten information bits to form the information word for coding via the �20, 10� code.
12. A coding circuit for coding information using a code having a fixed information word length, the coding circuit comprising one or more processing circuits configured to:
receive a number of input information bits less than the fixed information word length for forming an information word, the received input information bits being of one or more types;
add error protection bits to the received input information bits to make an information word length of the information word match the fixed information word length of the code, said error protection bits generated for a prioritized subset of the received input information bits by sub-coding the prioritized subset, for subsequent further coding as part of the information word; and
code the information word using the code to form a corresponding code word.
13. The coding circuit of claim 12, wherein the code is a systematic code.
14. The coding circuit of claim 13, wherein the code is a punctured quadratic residual code.
15. The coding circuit of claim 12, wherein the coding circuit is configured to generate the error protection bits as parity bits for the prioritized subset of input information bits.
16. The coding circuit of claim 12, wherein the coding circuit is configured to perform said receiving, adding, and coding in a second mode of operation, and is configured, in a first mode of operation, to receive a number of input information bits equal to the fixed information word length for forming a different information word, refrain from adding error protection bits to those received input information bits for making an information word length of the different information word match the fixed information word length of the code, and code the different information word using the code to form a corresponding code word.
17. The coding circuit of claim 16, wherein the coding circuit is configured for use in a Wideband Code Division Multiple Access (WCDMA) transceiver and the first and second modes of operation of the coding circuit comprise first and second modes of Multiple-Input-Multiple-Output (MIMO) operation, and wherein the number of input information bits received by the coding circuit include a first number of channel quality information bits in the first mode of operation and include a reduced, second number of channel quality information bits in the second mode of operation.
18. The coding circuit of claim 17, wherein the coding circuit is configured to receive input information bits in both the first and second modes of operation that include a set of channel quality information bits and a set of antenna pre-coding information bits, wherein the channel quality information bits are prioritized over the antenna pre-coding information bits, and wherein said adding in the second mode of operation comprises adding error protection bits for all or a subset of the channel quality information bits in the input information bits.
19. The coding circuit of claim 12, wherein the coding circuit is configured to receive input information bits including two or more types of input information bits, with one type being prioritized over the other type or types.
20. The coding circuit of claim 19, wherein the coding circuit is configured to add error protection bits by sub-coding all or a selected subset of the prioritized type of input information bits to produce the number of error protection bits needed to make the information word length of the information word match the fixed information word length.
21. The coding circuit of claim 19, wherein the coding circuit is configured to generate the error protection bits as a function of all or a subset of the prioritized type of input information bits.
22. The coding circuit of claim 12, wherein the code used by the coding circuit comprises a �20, 10� code having a code word length of twenty bits and a fixed information word length of ten bits, and wherein the coding circuit is configured to receive ten input information bits in a first mode of operation and therefore does not add error protection bits to form the information word, and in a second mode of operation to receive less than ten input information bits and therefore adds error protection bits to thereby obtain ten information bits for forming the information word for coding via the �20, 10� code.
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