WO2008094121A1

5G,4G

Title

METHOD FOR ADDING ERROR PROTECTION BITS TO MATCH CODEWORD LENGTH

Application Number:

WO2008SE50113

Publication Date:

07-08-2008

Current Assignee:

Family ID:

Application Date:

29-01-2008

Publication Country:

US

Priority Date:

30-01-2007

Declaring Company:

Abstract  Abstract

Teachings presented herein provide a method (100) and apparatus (10) for processing input information bits (16) for coding using a code (20) such that the length of the information word (14) formed from the input information bits (16) matches a fixed information word length defined by the code 20. In at least one embodiment a coding circuit (10) receives input information bits (16) and adds error protection bits (26) as needed to make the information word length match the fixed information word length. The method (100) and apparatus (10) contemplate generating the error protection bits (26) by sub-coding a subset (28) of the input information bits (26) (e.g. parity bit generation) thereby providing extra protection for that subset (28). These teachings allow the same code (20) to be used for coding feedback or other information where the amount of information to be coded varies as a function of operating modes.

Note:

The information in blue was extracted from the third parties (Standard Setting Organisation, Espacenet)

The information in grey was provided by the patent holder

The information in purple was extracted from the FrandAvenue

Explicitly disclosed patent:openly and comprehensibly describes all details of the invention in the patent document.

Implicitly disclosed patent:does not explicitly state certain aspects of the invention, but still allows for these to be inferred from the information provided.

Basis patent:The core patent in a family, outlining the fundamental invention from which related patents or applications originate.

Family member:related patents or applications that share a common priority or original filing.